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MRF49XA
REGISTER 2-15:
DCSREG: DUTY CYCLE VALUE SET REGISTER (POR: 0xC80E)
W-1
W-1
W-0
W-0
W-1
W-0
W-0
W-0
CCB<15:8>
bit 15
bit 8
W-0
W-0
W-0
W-0
W-1
W-1
W-1
W-0
bit 7
DCMV<6:0>
DCMEN
bit 0
Legend:
r = reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7-1
bit 0
Note 1:
CCB<15:8>: Command Code bits
The command code bits ( 11001000b ) are serially sent to the microcontroller to identify the bits to be
written in the DCSREG.
DCMV<6:0>: Duty Cycle Multiplier Value bits
These bits are used to calculate the duty cycle or on time of the receiver after the wake-up timer has
brought the MRF49XA out of Sleep mode (1) .
DCMEN: Duty Cycle mode Enable bit
1 = Enables the Duty Cycle mode
0 = Disables the Duty Cycle mode
For operation in Duty Cycle mode, the receiver must be disabled (RXCEN = 0 ) and the wake-up timer
must be enabled (WUTEN = 1 ) in PMCREG. The registers, DCSREG and WTSREG, can be used to
reduce the current consumption of the receiver. The DCSREG can be set up so that when the wake-up
timer brings the MRF49XA out of Sleep mode, the receiver is turned on for a short period to sample the
signal presence before returning to Sleep. The process in the Duty Cycle mode starts over. The duty cycle
uses the multiplier value of the wake-up timer, in parts for its calculation, as shown in Equation 2-8 .
EQUATION 2-8:
DC = [(DCMV<7:1> x 2 + 1)]/[WTMV<7:0> x 100%]
where:
WTMV is WTMV<7:0> bits of the WTSREG.
? 2009-2011 Microchip Technology Inc.
Preliminary
DS70590C-page 39
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